Voltage multipliers are commonly used to increase the voltage of a supply source in order to provide the higher voltages needed to operate circuit elements. One type of voltage multiplier is termed a charge pump, and is commonly used in non-volatile memory systems to provide the voltages needed for programming and erasing memory cells. A charge pump functions by progressively storing more charge on a capacitor which is part of a capacitor-diode combination, with several such stages being placed together in a network to obtain the desired increase in voltage. The diode functions to prevent discharge of the capacitor prior to its having additional charge placed on it. In charge pump designs which are fabricated using integrated circuit processing methods, both the diode and the capacitor are typically formed from properly configured transistors.
A clock signal is used to trigger the charging of the capacitor(s), with the clock frequency being such that the clock signal period is less than the discharge time of the capacitor(s). Typically, two clock signals having opposite phase are used to charge alternate stages of a multi-stage charge pump. The opposite phase clock signals are used to increase the amount of charge which can be placed on the capacitors.
FIG. 1 is a block diagram showing the components of a typical charge pump 10. Charge pump 10 includes oscillator 12 which is used to trigger the production of the clock signals by clock generator 14. The operation of oscillator 12 is initiated by enable signal 13. Clock generator 14 outputs the clock signals used to control the charging of the capacitors contained in pump circuit 16. Regulator 18 samples the output 17 of pump circuit 16 and generates reset signal 19 when pump circuit 16 outputs the appropriate voltage. Regulator 18 is used to control the operation of oscillator 12 in order to cause output 17 of pump circuit 16 to approach the desired output voltage. This is accomplished by turning oscillator 12 on or off, which in turn affects the frequency of the clock signals produced by clock generator 14.
FIG. 2A is a schematic diagram of a pump circuit 20 which can be used as part of a voltage multiplier, such as the charge pump of FIG. 1. The circuit of FIG. 2A is representative of that found in pump circuit 16 of FIG. 1. As shown in FIG. 2, the inputs to the circuit are an input supply voltage 22 and two clock signals, shown as Ph 1 23 and Ph 2 24 in the figure. As shown in FIG. 2B, clock signals 23 and 24 are typically square waves having opposite phases and an amplitude corresponding to the magnitude of external power supply 22. Input supply voltage 22 provides the supply of charge for the charge pump.
Clock signals 23 and 24 are connected to alternating stages of charge pump circuit 20, where each stage is composed of a transistor 26 configured to function as a diode, a pump capacitor 28 (labelled "C" in the figure), and a stray capacitance 30 representing the parasitic capacitance between node 27 (the charged node for that pump stage) and the substrate (labelled "C.sub.s " in the figure). Transistor 26 is typically configured to act as a diode by connecting the gate to the drain. Clock signal 23 or 24 is connected to one side of pump capacitor 28, with the other side of the capacitor being connected to the diode (transistor).
As shown in the figure, a total of N such stages are connected in a serial manner, eventually producing output voltage 32. Each stage has a diode, pump capacitor, and stray capacitance, as well as an associated clock signal. Pump capacitor 28 is typically implemented in the form of a properly configured transistor. In such a case, there is an additional stray capacitance associated with the configured transistor, the associated routing, and adjacent devices. This may be termed the stray capacitance on the clock driver side of the pump capacitor. Note that as before, there is a stray capacitance on the pumped node side (the capacitance labelled C.sub.s in FIG. 2A). This clock driver side stray capacitance must be charged and discharged with each cycling of the stages of the charge pump, thereby increasing the power required to operate the pump.
The efficiency of charge pump circuit 20 is determined by the ratio of the output power to input power, and is given by: ##EQU1## EQU V.sub.out =V.sub.supply +N.multidot.[C/(C+C.sub.s).multidot.V.sub.supply -VTN]-VTN-V.sub.dl,
where
V.sub.supply =Supply voltage to the pump circuit (Input); PA1 N=number of charge pump stages; PA1 VTN=voltage drop across the diode in a pump stage; PA1 V.sub.dl =voltage drop due to the load current (depends upon N, clock frequency, load current, diode resistance, and pump stage capacitance); PA1 C=pump capacitance per stage; and PA1 C.sub.s =stray capacitance per stage on the pumped node side.
Inspection of the expression for the pump efficiency shows that the efficiency may be increased by increasing V.sub.out or by decreasing I.sub.supply for a given number of stages. Previous attempts to increase the efficiency have focused on increasing V.sub.out. This has been accomplished by use of threshold cancellation techniques (such as those which will be described with reference to FIG. 3) and/or by using transistors having lower threshold voltages for the pump stage diodes. However, a disadvantage to using lower threshold voltage transistors is that they require additional manufacturing steps. V.sub.out can also be increased by reducing C.sub.s, which can be accomplished by optimizing the physical implementation of the charge pump.
FIG. 3A is a schematic diagram for a pump circuit 50 which uses the technique of Vt (threshold voltage) cancellation to increase the output voltage (and hence efficiency) of a charge pump. The threshold voltage of a transistor configured to act as a diode corresponds to the VTN voltage drop term in the expression for the pump efficiency. As shown in FIG. 3A, four clock signals, labelled Ph 1 52, Ph 1a 54, Ph 2 56, and Ph 2a 58 in FIG. 3B, are now used to control the operation of the circuit. As indicated in timing diagram FIG. 3B, clock signals Ph 1 52 and Ph 2 56 are typically square waves having opposite phase, while clock signals Ph 1a 54 and Ph 2a 58 are square waves that have a duty cycle that is smaller than that of signals Ph 1 and Ph 2. Signals Ph 1a 54 and Ph 2a 58 are square waves with a shorter time at which they have a high value than do signals Ph 1 and Ph 2.
Each stage of pump circuit 50 of FIG. 3A is composed of a switching transistor 60 (labelled "A" in the figure), a capacitor 62 connected between the gate of that transistor and a clock signal, a transistor 64 (labelled "B" in the figure) configured to act as a diode when transistor 60 is switched "on", and a pump capacitor 66 (labelled "C" in the figure). Capacitor 68 (labelled "C.sub.s " in the figure) represents the stray capacitance on the charged node side for the stage of the circuit. Capacitor 76 (labelled "C.sub.c " in the figure) represents the stray capacitance of pump capacitor 66 on the clock side of the circuit, which arises in the case where pump capacitor 66 is implemented in the form of a properly configured transistor or another fabricated capacitor.
In the operation of circuit 50, at time t1 (see FIG. 3B), clock signal Ph 1 52 goes high, charging capacitor 66 and causing the node labelled "STAGE 1" to be pumped by an amount which depends upon the ratio of C and C.sub.s. This causes transistor 60 to turn on, thereby connecting input supply voltage 70 to the node labelled VG1. After clock signal Ph 1 52 goes low, and at time t2, clock signal Ph 2a 58 goes high, charging capacitor 62 and pumping node VG1. This raises the voltage at node VG1 above input supply level 70.
The pumping of node VG1 causes transistor 64 to turn on, charging node STAGE 1 to input supply level 70. The Vt cancellation stage composed of transistor 60, capacitor 62, and clock signal Ph 2a 58 compensates for the threshold voltage (Vt) drop across transistor 64. In the absence of the cancellation stage, the threshold voltage drop would cause the voltage at node STAGE 1 to be (input supply 70-Vt). The cancellation technique serves to increase the voltage available at node STAGE 1 for use as the baseline voltage for the next pump stage.
At time t3 shown in timing diagram 3B, node STAGE 1 has been set to input supply level 70. This node is pumped up from this level on the rising edge of clock signal Ph 1 52. Clock signal Ph 2 56 and Ph 1a 54 are then used as shown in the timing diagram to increase the voltage at STAGE 2 by means of a second stage of pump circuit 50. The second stage operates in the same manner as the first stage which has been described, with the exception that instead of pre-charging the stage to a level corresponding to the input supply (corresponding to setting node VG1 to input level 70), node VG2 is pre-charged to a level equal to that of the voltage at node STAGE 1. This is accomplished by using clock signal Ph 2 56 to charge capacitor 67, thereby turning on switching transistor 61 and connecting node STAGE 1 to node VG 2. Clock signal Ph 1a 54 is then used to charge capacitor 63, pumping node VG2. This turns on transistor 65, charging node STAGE 2 to the level corresponding to node STAGE 1 (instead of the value STAGE 1-Vt, where Vt is the threshold voltage drop of transistor 65).
Note that although only two pump stages are shown in FIG. 3A, a greater number may of course be used. Each stage will contain a Vt cancellation circuit of the type shown, with the accompanying clock signals. At the end of the stages an output transistor 72 which is configured to act as a diode is used to shield the final pumped voltage from the load or output capacitance connected at output node 74.
Although the Vt cancellation charge pump circuit of FIG. 3A is an improvement over that of the standard circuit shown in FIG. 2, it still has some inefficient aspects. In particular, each stage requires the charging and discharging of capacitor 76, which has a capacitance dependent upon the structure of the transistor (or other form of capacitor) from which it is made. The charging and discharging represents work which is performed to operate the circuit, and since the discharged charge is conducted to ground, it is an expenditure of power which is not recaptured in later cycles of the pump. This causes an increase in the magnitude of I.sub.supply over what would be required in the absence of such a capacitance, and hence an increase in the power required to operate the circuit. This reduces the efficiency of the charge pump circuit. One way to address this problem is to use capacitor designs which limit the stray capacitance of the device, e.g., poly-poly capacitors. However, in most instances this approach is undesirable as it requires additional manufacturing steps, increasing the cost of the charge pump.
Although the increased power required to charge and discharge capacitor 76 (the stray capacitance on the clock side of the circuit) has been described with reference to the operation of a charge pump, this problem is also found in other types of circuits. In particular, any system or circuit having internal signals or nodes in opposite phase to each other may exhibit this behavior. Any circuit in which opposite phase signals act to charge and discharge an associated stray capacitance will require greater power to operate as a result of this situation.
What is desired is a charge pump circuit for use in generating higher voltages from a lower input supply voltage which is more efficient than existing charge pump circuits. This is particularly important in applications where the load current is small and power consumption is a critical concern. It is also desired to have an apparatus and method for reducing the power consumption of systems in which opposite phase signals which charge and discharge an associated stray capacitance are used as part of a circuit.